INTEL Logic Optimizing Compiler Utilization Report                   GNOME2.rpt
FIT Release [ 4.0 ] SID [ 268 ]


***** Design implemented successfully


******************************* ERROR REPORT *******************************


WARNING E7200-FITENGN: 5 Unused Input(s). They use a pin, but do not feed anything.
SIGNALS: UNUSED0, UNUSED1, UNUSED2, UNUSED3, UNUSED4


****************************** PART DESCRIPTION ******************************


         1             7
         1      1      5
         _______________
     12 |       o       | 74
        |               |
        |               |
        |               |
        |               |
        |               |
        |               |
     32 |_______________| 54
         3             5
         3             3
            EPX780LC84

*** CMOS Device:  Ground unused inputs and I/Os ***
     VCC   = VCC power (3 or 5 volt)             
     VCCoX = VCC power for CFB I/Os
     GND   = Connect to GND plane                 
     VPP   = Connect to VPP signal, VCC, or leave unconnected.
             Do NOT connect to GND.
     gnd   = an unused input or I/O pin.  Ensure termination

 V - represents signal voltage          O - represents an Open Drain output

PIN SIGNAL      V O PIN SIGNAL      V O PIN SIGNAL      V O PIN SIGNAL      V O 

1   LD_ACC         |22  PR9            |43  ACC0           |64  DRAM9          |
2   VCCo1          |23  GND            |44  VCCo6          |65  GND            |
3   (CLK1)         |24  VCCo2          |45  (CLK2)         |66  VCCo5          |
4   (VPP)          |25  VCCo0/4        |46  GND            |67  VCCo3/7        |
5   ACC3           |26  VCC            |47  CLOCK          |68  VCC            |
6   ACC2           |27  PC5            |48  RESET          |69  PC0            |
7   CARRY          |28  PC6            |49  UNUSED0        |70  PC1            |
8   WR_RAM_CLK     |29  GND            |50  UNUSED1        |71  GND            |
9   ALUMUX3        |30  ALUMUX1        |51  UNUSED2        |72  PC2            |
10  (TDO)          |31  ALUMUX2        |52  (TMS)          |73  PC3            |
11  (TDI)          |32  ALUMUX0        |53  (TCK)          |74  PC4            |
12  PR0            |33  ACC1           |54  DRAM0          |75  gnd            |
13  PR1            |34  S0             |55  DRAM1          |76  gnd            |
14  PR2            |35  S1             |56  DRAM2          |77  UNUSED3        |
15  PR3            |36  S2             |57  DRAM3          |78  UNUSED4        |
16  PR4            |37  S3             |58  DRAM4          |79  gnd            |
17  GND            |38  GND            |59  GND            |80  GND            |
18  PR5            |39  S4             |60  DRAM5          |81  gnd            |
19  PR6            |40  S5             |61  DRAM6          |82  WR_RAM         |
20  PR7            |41  S6             |62  DRAM7          |83  LD_C           |
21  PR8            |42  ZERO           |63  DRAM8          |84  LD_Z           |


****************************** PIN ASSIGNMENTS ******************************

**OUTPUTS**

Signal       Pin   V   D  Type   PTerms  [nu,up,lo,nl]  Blk  MCell

ALUMUX0      32           C      2       [ 0, 0, 1, 0]    4  9    
ALUMUX1      30           C      2       [ 0, 1, 0, 0]    4  5    
ALUMUX2      31           C      2       [ 0, 1, 0, 0]    4  7    
ALUMUX3      9            C      2       [ 0, 0, 1, 0]    0  9    
WR_RAM       82           C      1       [ 0, 0, 1, 0]    1  3    
WR_RAM_CLK   8            C      1       [ 0, 1, 0, 0]    0  7    
ACC0         43           D      6       [ 0, 1, 0, 0]    6  0    
ACC1         33           D      6       [ 0, 0, 1, 0]    6  9    
ACC2         6            D      6       [ 0, 1, 1, 1]    0  3    
ACC3         5            D      6       [ 0, 1, 0, 0]    0  0    
LD_ACC       1            C      5       [ 0, 1, 0, 0]    1  0    
ZERO         42           D      4       [ 0, 1, 0, 1]    6  1    
LD_Z         84           C      6       [ 0, 1, 1, 1]    1  1    
CARRY        7            D      3       [ 0, 1, 0, 1]    0  5    
LD_C         83           C      6       [ 1, 1, 1, 0]    1  2    
DRAM9        64           C(RAM)         [ 0, 0, 0, 0]    5  0    
DRAM8        63           C(RAM)         [ 0, 0, 0, 0]    5  1    
DRAM7        62           C(RAM)         [ 0, 0, 0, 0]    5  2    
DRAM6        61           C(RAM)         [ 0, 0, 0, 0]    5  3    
DRAM5        60           C(RAM)         [ 0, 0, 0, 0]    5  4    
DRAM4        58           C(RAM)         [ 0, 0, 0, 0]    5  5    
DRAM3        57           C(RAM)         [ 0, 0, 0, 0]    5  6    
DRAM2        56           C(RAM)         [ 0, 0, 0, 0]    5  7    
DRAM1        55           C(RAM)         [ 0, 0, 0, 0]    5  8    
DRAM0        54           C(RAM)         [ 0, 0, 0, 0]    5  9    
PC0          69           D      3       [ 0, 1, 0, 0]    3  0    
PC1          70           D      3       [ 0, 1, 0, 1]    3  3    
PC2          72           D      3       [ 0, 1, 0, 1]    3  5    
PC3          73           D      3       [ 0, 1, 0, 1]    3  7    
PC4          74           D      3       [ 0, 0, 1, 0]    3  9    
PC5          27           D      3       [ 0, 1, 0, 0]    4  0    
PC6          28           D      3       [ 0, 1, 0, 1]    4  3    
PR9          22           C(RAM)         [ 0, 0, 0, 0]    2  0    
PR8          21           C(RAM)         [ 0, 0, 0, 0]    2  1    
PR7          20           C(RAM)         [ 0, 0, 0, 0]    2  2    
PR6          19           C(RAM)         [ 0, 0, 0, 0]    2  3    
PR5          18           C(RAM)         [ 0, 0, 0, 0]    2  4    
PR4          16           C(RAM)         [ 0, 0, 0, 0]    2  5    
PR3          15           C(RAM)         [ 0, 0, 0, 0]    2  6    
PR2          14           C(RAM)         [ 0, 0, 0, 0]    2  7    
PR1          13           C(RAM)         [ 0, 0, 0, 0]    2  8    
PR0          12           C(RAM)         [ 0, 0, 0, 0]    2  9    
S6           41           C      4       [ 0, 1, 0, 1]    6  2    
S5           40           C      4       [ 0, 1, 0, 1]    6  3    
S4           39           C      4       [ 0, 1, 0, 1]    6  4    
S3           37           C      3       [ 0, 1, 0, 1]    6  5    
S2           36           C      3       [ 0, 1, 0, 1]    6  6    
S1           35           C      3       [ 0, 1, 0, 1]    6  7    
S0           34           C      4       [ 0, 1, 0, 1]    6  8    


**BURIED MACROCELLS**

Signal       Pin   V   D  Type   PTerms  [nu,up,lo,nl]  Blk  MCell

IMM_SEL      81           C      2       [ 0, 1, 0, 0]    1  4    
ADD          75           C      1       [ 0, 0, 1, 0]    1  9    
PASS         IO42         C      1       [ 0, 1, 0, 0]    4  2    
CLR_C        79           C      1       [ 0, 1, 0, 0]    1  5    
SET_C        78           C      1       [ 0, 1, 0, 0]    1  6    
C0           IO04         C      1       [ 0, 1, 0, 0]    0  4    
C1           IO41         C      3       [ 0, 1, 0, 1]    4  1    
C2           IO02         C      3       [ 0, 1, 0, 1]    0  2    
C3           IO01         C      3       [ 0, 1, 0, 1]    0  1    
JUMP         IO44         C      1       [ 0, 1, 0, 0]    4  4    
SKIP         77           C      2       [ 0, 1, 0, 0]    1  7    
SKIP_C       76           C      1       [ 0, 1, 0, 0]    1  8    
PC_C0        IO06         C      2       [ 0, 1, 0, 0]    0  6    
PC_C1        IO36         C      1       [ 0, 1, 0, 0]    3  6    
PC_C2        IO32         C      1       [ 0, 1, 0, 0]    3  2    
PC_C3        IO31         C      1       [ 0, 1, 0, 0]    3  1    
PC_C4        IO34         C      1       [ 0, 1, 0, 0]    3  4    
PC_C5        IO38         C      1       [ 0, 1, 0, 0]    3  8    
PC_C6        IO46         C      1       [ 0, 1, 0, 0]    4  6    


**INPUTS**

Signal         Pin  V  Level Blk

CLOCK          47               
RESET          48               
UNUSED0        49               
UNUSED1        50               
UNUSED2        51               
UNUSED3        77               
UNUSED4        78               


**UNUSED RESOURCES**

      Pin  Macrocell                     Pin  Macrocell

        -    IO08                         81    -                     
       79    -                            76    -                     
       75    -                             -    IO48                  
        -    IO70                          -    IO71                  
        -    IO72                          -    IO73                  
        -    IO74                          -    IO75                  
        -    IO76                          -    IO77                  
        -    IO78                          -    IO79                  
        3    -       (CLK1      )         45    -       (CLK2      )  

        6  : 12  Totals unused


****************************** CFB INFORMATION ******************************



**CFB Descriptions**

 CFB #
 0                   1                   2                   3                  
--------------------------------------------------------------------------------
IO00  ACC3         |IO10  LD_ACC       |IO20  PR9          |IO30  PC0          |
IO03  ACC2         |IO11  LD_Z         |IO21  PR8          |IO33  PC1          |
IO05  CARRY        |IO12  LD_C         |IO22  PR7          |IO35  PC2          |
IO01  C3           |IO13  WR_RAM       |IO23  PR6          |IO37  PC3          |
IO02  C2           |IO14  IMM_SEL      |IO24  PR5          |IO39  PC4          |
IO04  C0           |IO15  CLR_C        |IO25  PR4          |IO31  PC_C3        |
IO07  WR_RAM_CLK   |IO16  SET_C        |IO26  PR3          |IO32  PC_C2        |
IO06  PC_C0        |IO17  SKIP         |IO27  PR2          |IO34  PC_C4        |
IO09  ALUMUX3      |IO18  SKIP_C       |IO28  PR1          |IO36  PC_C1        |
                   |IO19  ADD          |IO29  PR0          |IO38  PC_C5        |


 CFB #
 4                   5                   6                   7                  
--------------------------------------------------------------------------------
IO40  PC5          |IO50  DRAM9        |IO62  S6           |                   |
IO43  PC6          |IO51  DRAM8        |IO63  S5           |                   |
IO41  C1           |IO52  DRAM7        |IO64  S4           |                   |
IO45  ALUMUX1      |IO53  DRAM6        |IO65  S3           |                   |
IO47  ALUMUX2      |IO54  DRAM5        |IO66  S2           |                   |
IO49  ALUMUX0      |IO55  DRAM4        |IO67  S1           |                   |
IO42  PASS         |IO56  DRAM3        |IO68  S0           |                   |
IO44  JUMP         |IO57  DRAM2        |IO60  ACC0         |                   |
IO46  PC_C6        |IO58  DRAM1        |IO69  ACC1         |                   |
                   |IO59  DRAM0        |IO61  ZERO         |                   |


**CFB Control Signals**

CFB # 0 Controls
Signal                     Equation
------------               --------
Sync. Clock 1        :  -
Sync. Clock 2        :  -
Async. Clock 1 pterm : /CARRY.ACLK
Async. Clock 2 pterm : /ACC2.ACLK
C/P 1 product term   : CARRY.RSTF
C/P 2 product term   : CARRY.SETF


CFB # 3 Controls
Signal                     Equation
------------               --------
Sync. Clock 1        :  -
Sync. Clock 2        :  -
Async. Clock 1 pterm : PC4.ACLK
C/P 1 product term   : PC4.RSTF


CFB # 4 Controls
Signal                     Equation
------------               --------
Sync. Clock 1        :  -
Sync. Clock 2        :  -
Async. Clock 1 pterm : PC6.ACLK
C/P 1 product term   : PC6.RSTF


CFB # 6 Controls
Signal                     Equation
------------               --------
Sync. Clock 1        :  -
Sync. Clock 2        :  -
Async. Clock 1 pterm : /ZERO.ACLK
Async. Clock 2 pterm : /ACC1.ACLK




**CFB fanins**

         | CFB #
         |  0                1                2                3              
------------------------------------------------------------------------------
%0       | LD_ACC.FB      | PR6.FB         |                | CLOCK.INT      |
%1       | CLOCK.INT      | PR5.FB         |                | RESET.INT      |
%2       | ACC3.FB        | PR4.FB         |                | JUMP           |
%3       | PASS           | PR8.FB         |                | PR0.FB         |
%4       | ALUMUX3.FB     | PR7.FB         | PC0.FB         | PC0.FB         |
%5       | C3             | PR9.FB         | PC1.FB         | PC_C0          |
%6       | ACC2.FB        |                | PC2.FB         | PR1.FB         |
%7       | ALUMUX2.FB     |                | PC3.FB         | PC1.FB         |
%8       | C2             |                | PC4.FB         | PC_C1          |
%9       | LD_C.FB        |                | GND            | PR2.FB         |
%10      | SET_C          |                | VCC            | PC2.FB         |
%11      | CLR_C          |                | GND            | PC_C2          |
%12      | ADD            |                | PC5.FB         | PR3.FB         |
%13      | ALUMUX1.FB     |                | PC6.FB         | PC3.FB         |
%14      | ACC1.FB        |                | VCC            | PC_C3          |
%15      | C1             |                | VCC            | PR4.FB         |
%16      | CARRY.FB       |                | VCC            | PC4.FB         |
%17      | WR_RAM.FB      |                | VCC            | PC_C4          |
%18      | SKIP           |                | VCC            |                |
%19      | SKIP_C         |                | VCC            |                |
%20      | ZERO.FB        |                | VCC            |                |
%21      | IMM_SEL        |                | VCC            |                |
%22      | PR3.FB         |                | VCC            |                |
%23      | DRAM3.FB       |                | VCC            |                |


         | CFB #
         |  4                5                6                7              
------------------------------------------------------------------------------
%0       | CLOCK.INT      |                | ACC3.FB        |                |
%1       | RESET.INT      |                | ACC2.FB        |                |
%2       | JUMP           |                | ACC1.FB        |                |
%3       | PR5.FB         |                | ACC0.FB        |                |
%4       | PC5.FB         | GND            | LD_ACC.FB      |                |
%5       | PC_C5          | GND            | CLOCK.INT      |                |
%6       | PR6.FB         | GND            | PASS           |                |
%7       | PC6.FB         | PR0.FB         | ALUMUX0.FB     |                |
%8       | PC_C6          | PR1.FB         | C0             |                |
%9       | ADD            | GND            | ALUMUX1.FB     |                |
%10      | ALUMUX0.FB     | WR_RAM_CLK.FB  | C1             |                |
%11      | ACC0.FB        | GND            | LD_Z.FB        |                |
%12      | C0             | PR2.FB         | ALUMUX3.FB     |                |
%13      | IMM_SEL        | PR3.FB         | ALUMUX2.FB     |                |
%14      | PR1.FB         | GND            |                |                |
%15      | DRAM1.FB       | GND            |                |                |
%16      | PR2.FB         | GND            |                |                |
%17      | DRAM2.FB       | GND            |                |                |
%18      | PR0.FB         | GND            |                |                |
%19      | DRAM0.FB       | GND            |                |                |
%20      | PR9.FB         | ACC3.FB        |                |                |
%21      | PR8.FB         | ACC2.FB        |                |                |
%22      | PR7.FB         | ACC1.FB        |                |                |
%23      |                | ACC0.FB        |                |                |

***************************** RAM DESCRIPTIONS *****************************


*** Description for DRAM ***

Number of address signals = 7
Number of output signals  = 10

PIN  SIGNAL        |PIN  SIGNAL        |PIN  SIGNAL        |PIN  SIGNAL        |
-------------------|-------------------|-------------------|-------------------|
IO50  DRAM9        |IO53  DRAM6        |IO56  DRAM3        |IO59  DRAM0        |
IO51  DRAM8        |IO54  DRAM5        |IO57  DRAM2        |                   |
IO52  DRAM7        |IO55  DRAM4        |IO58  DRAM1        |                   |


*** Description for PR ***

Number of address signals = 7
Number of output signals  = 10

PIN  SIGNAL        |PIN  SIGNAL        |PIN  SIGNAL        |PIN  SIGNAL        |
-------------------|-------------------|-------------------|-------------------|
IO20  PR9          |IO23  PR6          |IO26  PR3          |IO29  PR0          |
IO21  PR8          |IO24  PR5          |IO27  PR2          |                   |
IO22  PR7          |IO25  PR4          |IO28  PR1          |                   |


***************************** DESIGN STATISTICS *****************************

    Inputs ...........  7
    Outputs .......... 49
    Active Pins (in+out) .... 56

           Combinatorial.... 55
           D flip-flops .... 13
           T flip-flops ....  0
         J/K (emulation) ...  0
    Total Macrocells ............ 68         Buried Macrocells ... 19
    (includes SRAM Macrocells ... 20 )

    Largest Product Term ...  6
    Macrocell Product Terms (1-16): 15, 7, 14, 5, 1, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
    Total Product Terms >16       : 0

    SRAM Blocks ............  2

INTEL Logic Optimizing Compiler Utilization Report                   GNOME2.rpt
FIT Release [ 4.0 ] SID [ 268 ]

;--------------------------------------------------------
; THIS IS A PLDASM FILE THAT DESCRIBES THE GNOME.
; THE GNOME MICROCOMPUTER HAS:
;       + A 128X10 PROGRAM MEMORY
;       + A 7-BIT PROGRAM COUNTER
;       + A 16X4 DATA RAM
;       + A 4-BIT ACCUMULATOR
;       + A 4-BIT ALU
;       + A CARRY FLAG
;       + A ZERO FLAG
;--------------------------------------------------------
OPTIONS
    EXPAND = ON
    INVERSION = ON
    DT_SYNTHESIS = ON
    MINIMIZATION = ON
    FITTER_PINS = KEEP
    FITTER_PREV_PINS = ON
    FITTER_ALGORITHM = NORMAL
    SECURITY = OFF


;  ( part was NFX780_84 before conversion ) 
CHIP  GNOME2 EPX780LC84

PIN         47    CLOCK      
PIN         48    RESET      
PIN    [49:51]    UNUSED[0:2]
PIN    [77:78]    UNUSED[3:4]

PIN         32    ALUMUX0    
PIN    [30:31]    ALUMUX[1:2]
PIN          9    ALUMUX3    
NODE        81    IMM_SEL        CMBFBK
PIN         82    WR_RAM     
PIN          8    WR_RAM_CLK 
NODE        75    ADD            CMBFBK
NODE      IO42    PASS           CMBFBK
PIN         43    ACC0       
PIN         33    ACC1       
PIN      [6:5]    ACC[2:3]   
PIN          1    LD_ACC     
PIN         42    ZERO       
PIN         84    LD_Z       
PIN          7    CARRY      
NODE        79    CLR_C          CMBFBK
NODE        78    SET_C          CMBFBK
PIN         83    LD_C       
NODE      IO04    C0             CMBFBK
NODE      IO41    C1             CMBFBK
NODE      IO02    C2             CMBFBK
NODE      IO01    C3             CMBFBK
PIN    [64:60]    DRAM[9:5]      COMBINATORIAL    RAM
PIN    [58:54]    DRAM[4:0]      COMBINATORIAL    RAM
PIN    [69:70]    PC[0:1]    
PIN    [72:74]    PC[2:4]    
PIN    [27:28]    PC[5:6]    
NODE      IO44    JUMP           CMBFBK
NODE        77    SKIP           CMBFBK
NODE        76    SKIP_C         CMBFBK
NODE      IO06    PC_C0          CMBFBK
NODE      IO36    PC_C1          CMBFBK
NODE      IO32    PC_C2          CMBFBK
NODE      IO31    PC_C3          CMBFBK
NODE      IO34    PC_C4          CMBFBK
NODE      IO38    PC_C5          CMBFBK
NODE      IO46    PC_C6          CMBFBK
PIN    [22:18]    PR[9:5]        COMBINATORIAL    RAM
PIN    [16:12]    PR[4:0]        COMBINATORIAL    RAM
PIN    [41:39]    S[6:4]     
PIN    [37:34]    S[3:0]     

EQUATIONS

ALUMUX0 = IMM_SEL * PR0
        + /IMM_SEL * DRAM0
ALUMUX0.TRST = VCC

ALUMUX1 = IMM_SEL * PR1
        + /IMM_SEL * DRAM1
ALUMUX1.TRST = VCC

ALUMUX2 = IMM_SEL * PR2
        + /IMM_SEL * DRAM2
ALUMUX2.TRST = VCC

ALUMUX3 = IMM_SEL * PR3
        + /IMM_SEL * DRAM3
ALUMUX3.TRST = VCC

IMM_SEL = /PR9 * /PR8 * /PR7 * PR6 * PR4
        + /PR9 * /PR8 * /PR6 * /PR5 * PR4
IMM_SEL.TRST = GND

WR_RAM = /PR9 * /PR8 * /PR7 * /PR6 * PR5 * /PR4
WR_RAM.TRST = VCC

/WR_RAM_CLK = WR_RAM * CLOCK
WR_RAM_CLK.TRST = VCC

ADD = /PR9 * /PR8 * /PR7 * PR6 * /PR5
ADD.TRST = GND

PASS = /PR9 * /PR8 * /PR7 * /PR6 * /PR5
PASS.TRST = GND

ACC0.D := ACC0 * /PASS * /ALUMUX0 * /C0
        + ACC0 * /PASS * C0 * ALUMUX0
        + /ACC0 * ALUMUX0 * /C0
        + /ACC0 * /ALUMUX0 * C0
        + PASS * ALUMUX0 * /C0
        + PASS * /ALUMUX0 * C0
/ACC0.ACLK = /LD_ACC * CLOCK
ACC0.RSTF = GND
ACC0.SETF = GND
ACC0.TRST = VCC

ACC1.D := ACC1 * /PASS * /ALUMUX1 * /C1
        + ACC1 * /PASS * C1 * ALUMUX1
        + /ACC1 * ALUMUX1 * /C1
        + /ACC1 * /ALUMUX1 * C1
        + PASS * ALUMUX1 * /C1
        + PASS * /ALUMUX1 * C1
/ACC1.ACLK = /LD_ACC * CLOCK
ACC1.RSTF = GND
ACC1.SETF = GND
ACC1.TRST = VCC

ACC2.D := ACC2 * /PASS * /ALUMUX2 * /C2
        + ACC2 * /PASS * C2 * ALUMUX2
        + /ACC2 * ALUMUX2 * /C2
        + /ACC2 * /ALUMUX2 * C2
        + PASS * ALUMUX2 * /C2
        + PASS * /ALUMUX2 * C2
/ACC2.ACLK = /LD_ACC * CLOCK
ACC2.RSTF = GND
ACC2.SETF = GND
ACC2.TRST = VCC

ACC3.D := ACC3 * /PASS * /ALUMUX3 * /C3
        + ACC3 * /PASS * C3 * ALUMUX3
        + /ACC3 * ALUMUX3 * /C3
        + /ACC3 * /ALUMUX3 * C3
        + PASS * ALUMUX3 * /C3
        + PASS * /ALUMUX3 * C3
/ACC3.ACLK = /LD_ACC * CLOCK
ACC3.RSTF = GND
ACC3.SETF = GND
ACC3.TRST = VCC

LD_ACC = /PR6 * PR5 * /PR4 * /PR8 * /PR7
       + /PR6 * /PR5 * /PR4 * /PR9 * PR8 * /PR7
       + /PR6 * /PR5 * /PR9 * /PR8 * PR7
       + /PR4 * /PR9 * /PR8 * PR7
       + PR9 * /PR8 * /PR7
LD_ACC.TRST = VCC

/ZERO.D := ACC3 * ALUMUX3
         + ACC2 * ALUMUX2
         + ACC1 * ALUMUX1
         + ACC0 * ALUMUX0
/ZERO.ACLK = /LD_Z * CLOCK
ZERO.RSTF = GND
ZERO.SETF = GND
ZERO.TRST = VCC

LD_Z = /PR6 * /PR5 * /PR4 * /PR9 * /PR7
     + PR5 * /PR4 * /PR9 * /PR8
     + /PR5 * /PR8 * /PR7
     + PR6 * /PR4 * /PR9 * /PR8
     + PR6 * /PR8 * /PR7
     + PR9 * /PR8 * /PR7
LD_Z.TRST = VCC

CARRY.D := ALUMUX3 * ACC3
         + ALUMUX3 * C3
         + ACC3 * C3
/CARRY.ACLK = /LD_C * CLOCK
CARRY.RSTF = CLR_C
CARRY.SETF = SET_C
CARRY.TRST = VCC

CLR_C = /PR9 * /PR8 * PR7 * /PR6 * PR5 * /PR4
CLR_C.TRST = GND

SET_C = /PR9 * /PR8 * PR7 * PR6 * /PR5 * /PR4
SET_C.TRST = GND

LD_C = PR5 * /PR4 * /PR8 * /PR7
     + /PR6 * /PR5 * /PR4 * /PR9 * /PR7
     + PR6 * PR5 * /PR8 * /PR7
     + /PR6 * /PR5 * /PR9 * /PR8
     + /PR4 * /PR9 * /PR8 * PR7
     + PR9 * /PR8 * /PR7
LD_C.TRST = VCC

C0 = ADD * CARRY
C0.TRST = GND

C1 = ADD * ALUMUX0 * ACC0
   + ADD * ALUMUX0 * C0
   + ADD * ACC0 * C0
C1.TRST = GND

C2 = ADD * ALUMUX1 * ACC1
   + ADD * ALUMUX1 * C1
   + ADD * ACC1 * C1
C2.TRST = GND

C3 = ADD * ALUMUX2 * ACC2
   + ADD * ALUMUX2 * C2
   + ADD * ACC2 * C2
C3.TRST = GND

/DRAM.BE = GND
/DRAM.WE = WR_RAM_CLK
DRAM[3:0].ADDR = PR[3:0]
DRAM[6:4].ADDR = GND
/DRAM[3:0].TRST = GND
DRAM[9:4].DATA = GND
DRAM[3:0].DATA = ACC[3:0]

PC0.D := JUMP * PR0
       + /JUMP * PC0 * /PC_C0
       + /JUMP * /PC0 * PC_C0
PC0.ACLK = /CLOCK
PC0.RSTF = RESET
PC0.SETF = GND
PC0.TRST = VCC

PC1.D := JUMP * PR1
       + /JUMP * PC1 * /PC_C1
       + /JUMP * /PC1 * PC_C1
PC1.ACLK = /CLOCK
PC1.RSTF = RESET
PC1.SETF = GND
PC1.TRST = VCC

PC2.D := JUMP * PR2
       + /JUMP * PC2 * /PC_C2
       + /JUMP * /PC2 * PC_C2
PC2.ACLK = /CLOCK
PC2.RSTF = RESET
PC2.SETF = GND
PC2.TRST = VCC

PC3.D := JUMP * PR3
       + /JUMP * PC3 * /PC_C3
       + /JUMP * /PC3 * PC_C3
PC3.ACLK = /CLOCK
PC3.RSTF = RESET
PC3.SETF = GND
PC3.TRST = VCC

PC4.D := JUMP * PR4
       + /JUMP * PC4 * /PC_C4
       + /JUMP * /PC4 * PC_C4
PC4.ACLK = /CLOCK
PC4.RSTF = RESET
PC4.SETF = GND
PC4.TRST = VCC

PC5.D := JUMP * PR5
       + /JUMP * PC5 * /PC_C5
       + /JUMP * /PC5 * PC_C5
PC5.ACLK = /CLOCK
PC5.RSTF = RESET
PC5.SETF = GND
PC5.TRST = VCC

PC6.D := JUMP * PR6
       + /JUMP * PC6 * /PC_C6
       + /JUMP * /PC6 * PC_C6
PC6.ACLK = /CLOCK
PC6.RSTF = RESET
PC6.SETF = GND
PC6.TRST = VCC

JUMP = PR9 * /PR8 * /PR7
JUMP.TRST = GND

SKIP = /PR9 * /PR8 * PR7 * PR6 * PR5 * /PR4
     + /PR9 * PR8 * /PR7 * /PR6 * /PR5 * /PR4
SKIP.TRST = GND

SKIP_C = /PR9 * /PR8 * PR7 * PR6 * PR5 * /PR4
SKIP_C.TRST = GND

/PC_C0 = SKIP * SKIP_C * CARRY
       + SKIP * /SKIP_C * ZERO
PC_C0.TRST = GND

/PC_C1 = /PC0 * PC_C0
PC_C1.TRST = GND

PC_C2 = PC1 * PC_C1
PC_C2.TRST = GND

PC_C3 = PC2 * PC_C2
PC_C3.TRST = GND

PC_C4 = PC3 * PC_C3
PC_C4.TRST = GND

PC_C5 = PC4 * PC_C4
PC_C5.TRST = GND

PC_C6 = PC5 * PC_C5
PC_C6.TRST = GND

/PR.BE = GND
/PR.WE = VCC
PR[6:0].ADDR = PC[6:0]
/PR[9:0].TRST = GND
PR[9:0].DATA = VCC

/S6 = /ACC3 * ACC2 * /ACC1 * /ACC0
    + ACC3 * /ACC2 * ACC1 * ACC0
    + /ACC3 * /ACC2 * /ACC1 * ACC0
    + ACC3 * ACC2 * /ACC1 * ACC0
S6.TRST = VCC

/S5 = /ACC3 * /ACC2 * ACC1 * /ACC0
    + ACC3 * ACC2 * /ACC1 * ACC0
    + /ACC3 * /ACC2 * ACC0
    + /ACC3 * ACC1 * ACC0
S5.TRST = VCC

/S4 = /ACC3 * ACC2 * /ACC1 * ACC0
    + ACC3 * ACC1 * ACC0
    + ACC3 * ACC2 * /ACC0
    + ACC2 * ACC1 * /ACC0
S4.TRST = VCC

/S3 = /ACC3 * ACC2 * ACC1 * ACC0
    + ACC3 * ACC2 * /ACC1 * /ACC0
    + /ACC3 * /ACC2 * /ACC1
S3.TRST = VCC

/S2 = /ACC3 * ACC2 * /ACC1 * /ACC0
    + /ACC2 * /ACC1 * ACC0
    + /ACC3 * ACC0
S2.TRST = VCC

/S1 = /ACC3 * /ACC2 * ACC1 * /ACC0
    + ACC3 * ACC2 * ACC1
    + ACC3 * ACC2 * /ACC0
S1.TRST = VCC

/S0 = ACC3 * /ACC2 * ACC1 * /ACC0
    + /ACC3 * /ACC2 * /ACC1 * ACC0
    + /ACC3 * ACC2 * /ACC1 * /ACC0
    + ACC2 * ACC1 * ACC0
S0.TRST = VCC

RAM_DEFAULTS    PR
    0X00 : 0X014
    0X01 : 0X020
    0X02 : 0X015
    0X03 : 0X021
    0X04 : 0X01D
    0X05 : 0X022
    0X06 : 0X016
    0X07 : 0X023
    0X08 : 0X0A3
    0X09 : 0X000
    0X0A : 0X042
    0X0B : 0X024
    0X0C : 0X001
    0X0D : 0X043
    0X0E : 0X025
    0X0F : 0X20F

SIMULATION

    VECTOR ACC := [ ACC3 ACC2 ACC1 ACC0 ]
    VECTOR PC := [ PC6 PC5 PC4 PC3 PC2 PC1 PC0 ]
    VECTOR DRAM := [ DRAM3 DRAM2 DRAM1 DRAM0 ]
    VECTOR INSTR := [ PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 ]
    TRACE_ON PC INSTR DRAM ACC 
    SETF /CLOCK RESET 
    SETF /RESET 
    FOR I := 0 TO 16 DO
        BEGIN
        CLOCKF CLOCK 
        END
