INTEL Logic Optimizing Compiler Utilization Report                 COMPLE4B.rpt
FIT Release [ 4.0 ] SID [ 268 ]


***** Design implemented successfully


******************************* ERROR REPORT *******************************


WARNING E7200-FITENGN: 3 Unused Input(s). They use a pin, but do not feed anything.
SIGNALS: UNUSED0, UNUSED1, UNUSED2


****************************** PART DESCRIPTION ******************************


         1             7
         1      1      5
         _______________
     12 |       o       | 74
        |               |
        |               |
        |               |
        |               |
        |               |
        |               |
     32 |_______________| 54
         3             5
         3             3
            EPX780LC84

*** CMOS Device:  Ground unused inputs and I/Os ***
     VCC   = VCC power (3 or 5 volt)             
     VCCoX = VCC power for CFB I/Os
     GND   = Connect to GND plane                 
     VPP   = Connect to VPP signal, VCC, or leave unconnected.
             Do NOT connect to GND.
     gnd   = an unused input or I/O pin.  Ensure termination

 V - represents signal voltage          O - represents an Open Drain output

PIN SIGNAL      V O PIN SIGNAL      V O PIN SIGNAL      V O PIN SIGNAL      V O 

1   CP2            |22  gnd            |43  N78_CRY4       |64  gnd            |
2   VCCo1          |23  GND            |44  VCCo6          |65  GND            |
3   (CLK1)         |24  VCCo2          |45  (CLK2)         |66  VCCo5          |
4   (VPP)          |25  VCCo0/4        |46  GND            |67  VCCo3/7        |
5   CP1            |26  VCC            |47  A0             |68  VCC            |
6   N78_CRY1       |27  gnd            |48  A1             |69  gnd            |
7   INV0           |28  gnd            |49  A2             |70  gnd            |
8   INV1           |29  GND            |50  A3             |71  GND            |
9   COUT           |30  gnd            |51  UNUSED0        |72  gnd            |
10  (TDO)          |31  gnd            |52  (TMS)          |73  gnd            |
11  (TDI)          |32  gnd            |53  (TCK)          |74  gnd            |
12  gnd            |33  N78_CRY6       |54  gnd            |75  N78_CRY3       |
13  gnd            |34  S3             |55  gnd            |76  CP3            |
14  gnd            |35  S2             |56  gnd            |77  UNUSED1        |
15  gnd            |36  S1             |57  gnd            |78  UNUSED2        |
16  gnd            |37  S0             |58  gnd            |79  N78_CRY0       |
17  GND            |38  GND            |59  GND            |80  GND            |
18  gnd            |39  S4             |60  gnd            |81  CP0            |
19  gnd            |40  S5             |61  gnd            |82  INV3           |
20  gnd            |41  S6             |62  gnd            |83  INV2           |
21  gnd            |42  N78_CRY5       |63  gnd            |84  N78_CRY2       |


****************************** PIN ASSIGNMENTS ******************************

**OUTPUTS**

Signal       Pin   V   D  Type   PTerms  [nu,up,lo,nl]  Blk  MCell

INV0         7            C      1       [ 0, 1, 0, 0]    0  5    
INV1         8            C      1       [ 0, 1, 0, 0]    0  7    
INV2         83           C      1       [ 0, 1, 0, 0]    1  2    
INV3         82           C      1       [ 0, 1, 0, 0]    1  3    
CP0          81           C      1       [ 0, 1, 0, 0]    1  4    
N78_CRY0     79           C      1       [ 0, 1, 0, 0]    1  5    
CP1          5            C      2       [ 0, 1, 0, 0]    0  0    
N78_CRY1     6            C      1       [ 0, 1, 0, 0]    0  3    
CP2          1            C      2       [ 0, 1, 0, 0]    1  0    
N78_CRY2     84           C      1       [ 0, 1, 0, 0]    1  1    
CP3          76           C      2       [ 0, 1, 0, 0]    1  8    
N78_CRY3     75           C      1       [ 0, 0, 1, 0]    1  9    
N78_CRY4     43           C      0       [ 0, 0, 0, 0]    6  0    
N78_CRY5     42           C      0       [ 0, 0, 0, 0]    6  1    
N78_CRY6     33           C      0       [ 0, 0, 0, 0]    6  9    
COUT         9            C      0       [ 0, 0, 0, 0]    0  9    
S6           41           C      4       [ 0, 1, 0, 1]    6  2    
S5           40           C      4       [ 0, 1, 0, 1]    6  3    
S4           39           C      4       [ 0, 1, 0, 1]    6  4    
S3           34           C      3       [ 0, 1, 0, 1]    6  8    
S2           35           C      3       [ 0, 1, 0, 1]    6  7    
S1           36           C      3       [ 0, 1, 0, 1]    6  6    
S0           37           C      4       [ 0, 1, 0, 1]    6  5    


**INPUTS**

Signal         Pin  V  Level Blk

A0             47               
A1             48               
A2             49               
A3             50               
UNUSED0        51               
UNUSED1        77               
UNUSED2        78               


**UNUSED RESOURCES**

      Pin  Macrocell                     Pin  Macrocell

        -    IO01                          -    IO02                  
        -    IO04                          -    IO06                  
        -    IO08                          -    IO16                  
        -    IO17                         22    IO20                  
       21    IO21                         20    IO22                  
       19    IO23                         18    IO24                  
       16    IO25                         15    IO26                  
       14    IO27                         13    IO28                  
       12    IO29                         69    IO30                  
        -    IO31                          -    IO32                  
       70    IO33                          -    IO34                  
       72    IO35                          -    IO36                  
       73    IO37                          -    IO38                  
       74    IO39                         27    IO40                  
        -    IO41                          -    IO42                  
       28    IO43                          -    IO44                  
       30    IO45                          -    IO46                  
       31    IO47                          -    IO48                  
       32    IO49                         64    IO50                  
       63    IO51                         62    IO52                  
       61    IO53                         60    IO54                  
       58    IO55                         57    IO56                  
       56    IO57                         55    IO58                  
       54    IO59                          -    IO70                  
        -    IO71                          -    IO72                  
        -    IO73                          -    IO74                  
        -    IO75                          -    IO76                  
        -    IO77                          -    IO78                  
        -    IO79                          3    -       (CLK1      )  
       45    -       (CLK2      )  

       32  : 57  Totals unused


****************************** CFB INFORMATION ******************************



**CFB Descriptions**

 CFB #
 0                   1                   2                   3                  
--------------------------------------------------------------------------------
IO00  CP1          |IO10  CP2          |                   |                   |
IO03  N78_CRY1     |IO11  N78_CRY2     |                   |                   |
IO05  INV0         |IO12  INV2         |                   |                   |
IO07  INV1         |IO13  INV3         |                   |                   |
IO09  COUT         |IO14  CP0          |                   |                   |
                   |IO15  N78_CRY0     |                   |                   |
                   |IO18  CP3          |                   |                   |
                   |IO19  N78_CRY3     |                   |                   |
                   |                   |                   |                   |
                   |                   |                   |                   |


 CFB #
 4                   5                   6                   7                  
--------------------------------------------------------------------------------
                   |                   |IO62  S6           |                   |
                   |                   |IO63  S5           |                   |
                   |                   |IO64  S4           |                   |
                   |                   |IO65  S0           |                   |
                   |                   |IO66  S1           |                   |
                   |                   |IO67  S2           |                   |
                   |                   |IO68  S3           |                   |
                   |                   |IO60  N78_CRY4     |                   |
                   |                   |IO61  N78_CRY5     |                   |
                   |                   |IO69  N78_CRY6     |                   |


**CFB fanins**

         | CFB #
         |  0                1                2                3              
------------------------------------------------------------------------------
%0       | INV1.FB        | INV2.FB        |                |                |
%1       | N78_CRY0.FB    | N78_CRY1.FB    |                |                |
%2       | A0.INT         | A2.INT         |                |                |
%3       | A1.INT         | A3.INT         |                |                |
%4       |                | INV0.FB        |                |                |
%5       |                | INV3.FB        |                |                |
%6       |                | N78_CRY2.FB    |                |                |
%7       |                |                |                |                |
%8       |                |                |                |                |
%9       |                |                |                |                |
%10      |                |                |                |                |
%11      |                |                |                |                |
%12      |                |                |                |                |
%13      |                |                |                |                |
%14      |                |                |                |                |
%15      |                |                |                |                |
%16      |                |                |                |                |
%17      |                |                |                |                |
%18      |                |                |                |                |
%19      |                |                |                |                |
%20      |                |                |                |                |
%21      |                |                |                |                |
%22      |                |                |                |                |
%23      |                |                |                |                |


         | CFB #
         |  4                5                6                7              
------------------------------------------------------------------------------
%0       |                |                | CP3.FB         |                |
%1       |                |                | CP2.FB         |                |
%2       |                |                | CP1.FB         |                |
%3       |                |                | CP0.FB         |                |
%4       |                |                |                |                |
%5       |                |                |                |                |
%6       |                |                |                |                |
%7       |                |                |                |                |
%8       |                |                |                |                |
%9       |                |                |                |                |
%10      |                |                |                |                |
%11      |                |                |                |                |
%12      |                |                |                |                |
%13      |                |                |                |                |
%14      |                |                |                |                |
%15      |                |                |                |                |
%16      |                |                |                |                |
%17      |                |                |                |                |
%18      |                |                |                |                |
%19      |                |                |                |                |
%20      |                |                |                |                |
%21      |                |                |                |                |
%22      |                |                |                |                |
%23      |                |                |                |                |

***************************** DESIGN STATISTICS *****************************

    Inputs ...........  7
    Outputs .......... 23
    Active Pins (in+out) .... 30

           Combinatorial.... 23
           D flip-flops ....  0
           T flip-flops ....  0
         J/K (emulation) ...  0
    Total Macrocells ............ 23         Buried Macrocells ...  0
    (includes SRAM Macrocells ... 0 )

    Largest Product Term ...  4
    Macrocell Product Terms (1-16): 13, 3, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
    Total Product Terms >16       : 0

INTEL Logic Optimizing Compiler Utilization Report                 COMPLE4B.rpt
FIT Release [ 4.0 ] SID [ 268 ]

;MODIFIED FOR 4-BIT NUMBER 2'S COMPLEMENT WITH LEDDIGIT---------------------------------------------------------
; THIS IS A PLDASM FILE FOR A 7-BIT 2'S-COMPLEMENTER THAT
; USES THE PREVIOUSLY-DEFINED 8-BIT ADDER MODULE.
;---------------------------------------------------------
TITLE   COMPLEMENTER 4-BIT

OPTIONS
    EXPAND = ON
    INVERSION = ON
    DT_SYNTHESIS = ON
    MINIMIZATION = ON
    FITTER_PINS = TRY
    FITTER_PREV_PINS = OFF
    FITTER_ALGORITHM = NORMAL
    SECURITY = OFF


;  ( part was NFX780_84 before conversion ) 
CHIP  COMPLE4B EPX780LC84

PIN    [47:50]    A[0:3]      
PIN         51    UNUSED0     
PIN    [77:78]    UNUSED[1:2] 

PIN      [7:8]    INV[0:1]    
PIN    [83:82]    INV[2:3]    
PIN         81    CP0         
PIN         79    N78_CRY0    
PIN          5    CP1         
PIN          6    N78_CRY1    
PIN          1    CP2         
PIN         84    N78_CRY2    
PIN         76    CP3         
PIN         75    N78_CRY3    
PIN    [43:42]    N78_CRY[4:5]
PIN         33    N78_CRY6    
PIN          9    COUT        
PIN    [41:39]    S[6:4]      
PIN    [34:37]    S[3:0]      

EQUATIONS

INV0 = /A0
INV0.TRST = VCC

INV1 = /A1
INV1.TRST = VCC

INV2 = /A2
INV2.TRST = VCC

INV3 = /A3
INV3.TRST = VCC

CP0 = /INV0
CP0.TRST = VCC

N78_CRY0 = INV0
N78_CRY0.TRST = VCC

CP1 = INV1 * /N78_CRY0
    + /INV1 * N78_CRY0
CP1.TRST = VCC

N78_CRY1 = INV1 * N78_CRY0
N78_CRY1.TRST = VCC

CP2 = INV2 * /N78_CRY1
    + /INV2 * N78_CRY1
CP2.TRST = VCC

N78_CRY2 = INV2 * N78_CRY1
N78_CRY2.TRST = VCC

CP3 = INV3 * /N78_CRY2
    + /INV3 * N78_CRY2
CP3.TRST = VCC

N78_CRY3 = INV3 * N78_CRY2
N78_CRY3.TRST = VCC

N78_CRY4 = GND
N78_CRY4.TRST = VCC

N78_CRY5 = GND
N78_CRY5.TRST = VCC

N78_CRY6 = GND
N78_CRY6.TRST = VCC

COUT = GND
COUT.TRST = VCC

/S6 = /CP3 * CP2 * /CP1 * /CP0
    + CP3 * /CP2 * CP1 * CP0
    + /CP3 * /CP2 * /CP1 * CP0
    + CP3 * CP2 * /CP1 * CP0
S6.TRST = VCC

/S5 = /CP3 * /CP2 * CP1 * /CP0
    + CP3 * CP2 * /CP1 * CP0
    + /CP3 * /CP2 * CP0
    + /CP3 * CP1 * CP0
S5.TRST = VCC

/S4 = /CP3 * CP2 * /CP1 * CP0
    + CP3 * CP1 * CP0
    + CP3 * CP2 * /CP0
    + CP2 * CP1 * /CP0
S4.TRST = VCC

/S3 = /CP3 * CP2 * CP1 * CP0
    + CP3 * CP2 * /CP1 * /CP0
    + /CP3 * /CP2 * /CP1
S3.TRST = VCC

/S2 = /CP3 * CP2 * /CP1 * /CP0
    + /CP2 * /CP1 * CP0
    + /CP3 * CP0
S2.TRST = VCC

/S1 = /CP3 * /CP2 * CP1 * /CP0
    + CP3 * CP2 * CP1
    + CP3 * CP2 * /CP0
S1.TRST = VCC

/S0 = CP3 * /CP2 * CP1 * /CP0
    + /CP3 * /CP2 * /CP1 * CP0
    + /CP3 * CP2 * /CP1 * /CP0
    + CP2 * CP1 * CP0
S0.TRST = VCC

SIMULATION

    VECTOR IN_A := [ A3 A2 A1 A0 ]
    VECTOR COMP := [ CP3 CP2 CP1 CP0 ]
    TRACE_ON IN_A COMP 
    FOR I := 0 TO 15 DO
        BEGIN
        SETF IN_A := I 
        END
